By Shouri Chatterjee, K.P. Pun, Nebojša Stanic, Yannis Tsividis, Peter Kinget
This ebook tackles demanding situations for the layout of analog built-in circuits that function from ultra-low strength offer voltages (down to 0.5V). assurance demonstrates the sign processing circuit and circuit biasing techniques in the course of the layout of operational transconductance amplifiers (OTAs). those amplifiers are then used to construct analog process features together with non-stop time filter out and a pattern and carry amplifier.
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Additional info for Analog Circuit Design Techniques at 0.5V (Analog Circuits and Signal Processing)
This voltage, applied to the body of the nMOS device in the error amplifier, controls the threshold voltage of the nMOS devices in each error amplifier. Through an active feedback loop, Vamp is controlled to set the switching threshold voltage of the error amplifier to VDD /2, as shown in Fig. 12(a). 30(a) shows a single error amplifier. 30(a) is replaced with two nMOS devices, MN1 and MN2 , in Fig. 30(b). The input voltage is amplified by the devices MN1 and MP , while Vamp controls the current through MN2 .
25 V. This signal was applied to the circuit as an input. The Tektronix P6046 differential probe was used to sense the outputs of the OTA. Extensive measurements were taken using the HP3585A spectrum analyzer. To measure common-mode and powersupply rejection ratios, the setup shown in Fig. 18 was used. 3. 5 V, and is shown in comparison to simulated results in Fig. 19. Simulations of the open-loop phase response, adjusted for board parasitic capacitances, are shown compared to measurements, in Fig.
27: Harmonic distortion in the gate-input OTA, in closed loop, for different input amplitudes. 18 Lat. Lat. Depl. 4 GBW · CL Isupply A basic input stage of a gate-input OTA, as shown earlier in Fig. 8(b), but without the common-mode feed-forward structures, is shown in Fig. 28(a). An extension of this OTA stage, that takes full advantage of low-VT devices, and does not require access to the bodies of the devices, is shown in Fig. 28(b). The devices M1A and M1B in Fig. 28(a) are each replaced with two devices – M1A is replaced with a combination of M11A and M12A , and M1B is replaced with a combination of M11B and M12B .